In transistor level layout (e.g., of a metal oxide semiconductor (MOS) transistor), a length of diffusion (LOD) refers to an amount by which a diffusion region between source and drain terminals of the transistor extends away from a gate terminal. An LOD effect refers to stress induced on the MOS transistor based on the LOD. In general, a smaller LOD causes greater stress or in other words, has a worse LOD effect, while increasing or improving the LOD can lead to performance improvements.
It is difficult to completely mitigate LOD effect on transistors in a transistor level layout using standard logic cells and placement techniques. Some techniques to mitigate the LOD effect focus on extending the diffusion region, where possible, with left and right diffusion edges configured to share common electrical junctions (e.g., power and ground connections). However, extending the diffusion region in this manner may hinder cell placement methodologies which attempt to place logic cells of equal or comparable physical footprints (also measured in terms of cell pitch or width of the diffusion layers) in a manner which results in logic cells being abutted or adjoined. Such abutment can enable sharing of diffusion edges between adjoining cells and potentially increase the effective LOD of adjoining cells. However, logic cell placement to improve diffusion edge sharing in this manner may not be feasible in some situations.
For example, considering Fin Field Effect Transistor (Finfet) technologies wherein a common gate terminal may be shared among multiple Fins (or source/drain terminals of multiple FET cells), Finfet logic libraries may include logic cells with different Fin counts. If the diffusion regions of some Fins can be extended as noted above, the logic libraries may include logic cells with non-uniform lengths of diffusion regions, which means that some Fins of adjoining cells may not be able to share their diffusion regions with neighboring cells. Further, a lateral width of diffusion (in a transverse direction to the length of diffusion) varies proportionally with the number of Fins of each logic cell in a logic cell layout. While conventional layout techniques may allow for abutment of logic cells with the same number of Fins or the same width, such techniques may not permit placement of two cells with different Fin counts in a manner which could have allowed for sharing diffusion regions.
Accordingly, there is a need for improved logic cells and placement methodologies thereof which avoid the aforementioned problems of conventional techniques while mitigating LOD effects.